[Verilog] 기본 gate

https://hdlbits.01xz.net/wiki/Problem_sets

Problem sets - HDLBits

 

NOT

module top_module( input in, output out );
	
    assign out = !in;		// ~: bitwise, !: Logcial
    
endmodule

 

AND

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = a && b;		// &: bitwise, &&: Logical
    
endmodule

 

OR

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = a||b;		// |: bitwise, ||: Logical

endmodule

 

XOR

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = a^b;		// ^: bitwise		// No Logical

endmodule

※ 1의 개수가 홀수개 이면 1 그외 0

※ XOR은 Logical 연산이 없음

 

 

연습문제

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    
    wire in_or1, in_or2;
    
    assign in_or1 = a & b;
    assign in_or2 = c & d;
    
    assign out = in_or1 | in_or2;
    assign out_n = !(in_or1 | in_or2);
    

endmodule