[Verilog] Module

https://hdlbits.01xz.net/wiki/Problem_sets

Problem sets - HDLBits

 

 

Module_name

Connecting port by name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a u0(.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2));

endmodule

 

 

Module shift

module top_module ( input clk, input d, output q );
	
    wire q0;
    wire q1;
    
    my_dff u_0(.clk(clk), .d(d), .q(q0));
    my_dff u_1(.clk(clk), .d(q0), .q(q1));
    my_dff u_2(.clk(clk), .d(q1), .q(q));
    
endmodule

 

Module_shift8

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    
    wire [7:0] q0;
    wire [7:0] q1;
    wire [7:0] q2;
    
    my_dff8 u_0(.clk(clk), .d(d), .q(q0));
    my_dff8 u_1(.clk(clk), .d(q0), .q(q1));
    my_dff8 u_2(.clk(clk), .d(q1), .q(q2));

    
    always @(*)
    begin
        case(sel)
            // 2'd0 : q <= d;
            2'd1 : q <= q0;
            2'd2 : q <= q1;
            2'd3 : q <= q2;
            default : q <= d;		//default is more robust
        endcase
    end
    
    
endmodule

 

 

※ Full_adder

Half_adder의 경우 c_in이 없고 Full_adder의 경우 c_in이 있다

module Full_adder ( input a, input b, input c_in, output sum, output c_out);
    
    assign sum = a ^ b ^ c_in;
    assign c_out = (a & b) | (b & c_in) | (c_in & a);
    
endmodule