[Verilog] Basic Gate

https://hdlbits.01xz.net/wiki/Problem_sets

Problem sets - HDLBits

 

 

Popcount3

population count : 1의 개수

※ 7 = 0111(2) 따라서 3

module top_module( 
    input [2:0] in,
    output [1:0] out );
    
    assign out = in[0]+in[1]+in[2];

endmodule

 

 

Gatesv

out_both : 인접한 2비트가 둘다 1이면 1

out_any : 인접한 2비트가 둘중하나가 1이면 1

out_different : 인접한 2비트가 다르면 1

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );

    //assign out_both[0] = in[1] & in[0];
    //assign out_both[1] = in[2] & in[1];
    //assign out_both[2] = in[3] & in[2];
    assign out_both = in[3:1] & in[2:0];
    
    //assign out_any[1] = in[1] | in[0];
    //assign out_any[2] = in[2] | in[1];
    //assign out_any[3] = in[3] | in[2];
    assign out_any = in[3:1] | in[2:0];
    
    //assign out_different[0] = in[1] ^ in[0];
    //assign out_different[1] = in[2] ^ in[1];
    //assign out_different[2] = in[3] ^ in[2];
    //assign out_different[3] = in[0] ^ in[3];
    assign out_different = {in[0], in[3:1]} ^ in;

endmodule