[Verilog] Gate-Level에서 D Latch & D Flip-Flop

D Latch

CLK = 0 : Q(t+1) = D

CLK = 1 : Q(t+1) = Q(t)     <= 기존값 유지

`timescale 1ns / 1ps

module d_latch(
    input       D       ,
    input       CLK     ,
    output      Q       ,
    output      n_Q
);


    
    wire n_CLK;
    wire nand0, nand1;
    wire out0, out1;
    
    assign nand0 = ~(D & CLK);
    assign nand1 = ~(~D & CLK);
    
    assign out0 = Q;
    assign out1 = n_Q;
    
    assign Q = ~(nand0 & n_Q);
    assign n_Q = ~(nand1 & Q);
    
    
endmodule

d_latch.v

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tb_d_latch.v

0.00MB

 

4Nand, 1Inverter

※ Nand 1개당 Transistor 4개, Inverter 1개당 Transistor 2개 따라서 18Transistor 필요

 

 

D Flip-Flop

CLK = ↑ (Rising Edge) : Q(t+1) = D

CLK = 그외                  : Q(t+1) = Q(t)     <= 기존값 유지

`timescale 1ns / 1ps

module d_ff(
    input       D       ,
    input       CLK     ,
    output      Q       ,
    output      n_Q
    );
    
    wire Q0;
    
    
    d_latch u_d_latch0(
    .	D       (D),
    .	CLK     (~CLK),
    .	Q       (Q0),
    .	n_Q     ()
    );
    d_latch u_d_latch1(
    .	D       (Q0),
    .	CLK     (CLK),
    .	Q       (Q),
    .	n_Q     (n_Q)
    );
    
endmodule

d_ff.v

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tb_d_ff.v

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D Latch가 2개 사용되므로 8Nand, 2Inverter

※ 36Transistor

 

출처

https://m.blog.naver.com/study_together_/221277740243

[대학교 디지털시스템] 래치(Latch)/플립플롭(Flip-flop)

http://www.ktword.co.kr/test/view/view.php?m_temp1=4712 

D 플립플롭