[Verilog] Latches and Flip-floops

https://hdlbits.01xz.net/wiki/Problem_sets

Problem sets - HDLBits

 

 

Dff8

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);

    always @(posedge clk) begin
    	q <= d;
    end

endmodule

 

 

Dff8r

Synchronous reset

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    
    always @(posedge clk) begin
        if(reset)
            q <= 8'h00;
        else
            q <= d;
    end
    
endmodule

 

 

Dff8ar

Asynchronous reset

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);

    always @(posedge areset, posedge clk) begin
        if(areset)
            q <= 8'h00;
        else
            q <= d;
    end

endmodule