[Verilog] 125MHz -> 1KHz 분주기

zybo z7-20이 125MHz 이므로 1KHz 분주기를 설계했다.

 

코드

`timescale 1ns / 1ps
module pre_1khz(
    input				i_clk		,		// xdc's sysclk
	input				rst			,
	output reg			o_clk
    );

    
    reg [15:0] counter62500;        // 2^16 = 65536

	
	always @(posedge rst, posedge i_clk) begin
		
		if(rst) begin
			counter62500 <= 0;
			o_clk <= 0;
		end
		else if(counter62500<62499) begin
			counter62500 <= counter62500 + 1;
		end
		else begin
			counter62500 <= 0;
			o_clk = ~o_clk;
		end
	end
    
    
endmodule

 

testbench

`timescale 1ns / 1ps
module tb_pre_1khz(
    
    );
    
	reg i_clk	;
	reg rst		;
	wire o_clk  ;
    
    
    
    pre_1khz u0(
		.i_clk(i_clk),
		.rst(rst),
		.o_clk(o_clk)
    );
    
	always #4 i_clk = ~i_clk;		//125MHz = 8ns
    
	initial begin
		i_clk = 0;
		rst = 1;
		#1000 rst = 0;
	end
	
    
endmodule