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전자공학/디지털회로17

[Verilog] More Verilog Features https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net Reduction parity비트 짝수 패리티 : 1의 개수 짝수개 홀수 패리티 : 1의 개수 홀수개 따라서 XOR 이용해서 생성하기 module top_module ( input [7:0] in, output parity); //assign parity = ^in; assign parity = ^in[7:0]; endmodule ※ 아래 코드처럼 bit연산 가능함 module top_module( input [99:0] in, output out_and, output out_or, output out_xor ); assign out_and = ∈ as.. 2022. 12. 20.
[Verilog] Procedures https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net ※ begin/end문 begin 내에 있는 코드는 순서대로 실행된다 ※ Blocking vs Non-Blocking Blocking '=' 을 통해서 할당함, SW코드 처럼 순차적으로 실행됨, Combinational Logic ex) 원래 a==0 일 때 a = 1; b = a; 따라서 a와 b 모두 1이 존재 Non-Blocking ' 2022. 12. 15.
[Verilog] Module https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net Module_name Connecting port by name module top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a u0(.in1(a), .in2(b), .in3(c), .in4(d), .out1(out1), .out2(out2)); endmodule Module shift module top_module ( input clk, input d, output q ); wire q0; wire q1; my_dff u_0(.clk(clk), .d(d), ... 2022. 12. 14.
[Verilog] Vector https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net Vector1 `default_nettype none // Disable implicit nets. Reduces some types of bugs. module top_module( input wire [15:0] in, output wire [7:0] out_hi, output wire [7:0] out_lo ); assign out_hi = in[15:8]; assign out_lo = in[7:0]; endmodule Vector2 module top_module( input [31:0] in, output [31:0] out ); assign out.. 2022. 12. 13.

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