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전자공학/디지털회로17

[Verilog] Latches and Flip-floops https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net Dff8 module top_module ( input clk, input [7:0] d, output [7:0] q ); always @(posedge clk) begin q 2022. 12. 22.
[Verilog] Arithmetic Circuit https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net Hadd Half Adder(반가산기) module top_module( input a, b, output cout, sum ); assign cout = a & b; assign sum = a ^ b; endmodule Fadd Full Adder(전가산기) module top_module( input a, b, cin, output cout, sum ); assign cout = a&b | b&cin | cin&a; assign sum = a ^ b ^ cin; endmodule ※ Half Adder vs Full Adder carry_in이 있으면 F.. 2022. 12. 21.
[Verilog] Multiplexer https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net Mux2to1v sel 0이면 a, 1이면 b module top_module( input [99:0] a, b, input sel, output [99:0] out ); assign out = (sel? b: a); endmodule Mux9to1v sel 0:a, 1:b,..., 8:d 이고 그외는 1111_1111_1111_1111 module top_module( input [15:0] a, b, c, d, e, f, g, h, i, input [3:0] sel, output reg [15:0] out ); //always는 reg가 필요함 alway.. 2022. 12. 21.
[Verilog] Basic Gate https://hdlbits.01xz.net/wiki/Problem_sets Problem sets - HDLBits hdlbits.01xz.net Popcount3 population count : 1의 개수 ※ 7 = 0111(2) 따라서 3 module top_module( input [2:0] in, output [1:0] out ); assign out = in[0]+in[1]+in[2]; endmodule Gatesv out_both : 인접한 2비트가 둘다 1이면 1 out_any : 인접한 2비트가 둘중하나가 1이면 1 out_different : 인접한 2비트가 다르면 1 module top_module( input [3:0] in, output [2:0] out_both, output .. 2022. 12. 20.

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